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IEEE SSCS Taipei Chapter Short Course
A System's Approach to Building Modern High-Speed Links
Prof. Vladimir Stojanovic
Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
一、場次
<第一場> 國立交通大學光復校區工四館國際會議廳
1月31日(星期三) 9:00~12:00，13:30~16:30
<第二場> 國立台灣大學電機二館105視聽教室
2月01日(星期四) 9:00~12:00，14:00~17:00
二、報名日期
即日起至01月30日止；一律上網報名
http://powereric.ee.ntu.edu.tw/~sscs/lectures/stojanovic/index.html
三、報名費用
(含講義、午餐及點心，恕不退費)
IEEE Member Non-IEEE Member
業界 4000 4500
教師 1000 1500
學生 500 1000
四、繳費方式
(1) 請將支票或匯票掛號寄到『10617台北市大安區羅斯福路四段一號
國立台灣大學電機二館347室 李孋倫小姐收』。
(2) 支票或匯票抬頭『李孋倫』。
(3) 請在支票或匯票背面用鉛筆註明『單位』、『姓名』及『報名序號』。
(4) 請於01月30日前將支票或匯票寄達。
五、洽詢辦法
(1) 電話: (02)2363-5251 ext.367，李孋倫小姐。
(2) Email: necoppp@cc.ee.ntu.edu.tw
六、主辦單位
國立台灣大學電子工程研究所
IEEE SSCS Taipei Chapter
七、課程大綱
Over the past decade, high-speed interfaces have increased the data
rates from 100's Mb/s in early 90's to tens of Gb/s today. Until
recently, these data rate improvements were mostly due to innovations
in building the fast multiplexing transmitters and receivers that
overcome the inherent speed limitation of the IC technology and also
due to increasingly better clock generation and recovery. However,
today's high-speed interfaces are limited by the bandwidth of the
communication channel, tight power constraints and noise sources that
differ from those in standard communication systems. The wire bandwidth
limitations make straight circuit solutions inefficient, and the power
and area constraints make standard digital communication approaches
infeasible. Efficient solutions require bridging the fields of digital
communications, optimization, statistical and dynamic system modeling,
with system architecture, mixed-signal and digital circuit design.
This short course covers the system and design issues relevant to
modern high-speed electrical signaling. We start by introducing the
basics of channel properties, modeling, measurements, and communications
techniques. The system design issues such as planning and budgeting are
also presented. We then present the basics of link hardware components
like clock generation (PLL, DLL) and recovery, multiplexed drivers,
modulators and equalizers. System-driven circuit design of main
components is covered in detail. Using the insight from these link
models and circuits, we can drive the efficient implementation of
custom signal processing that is needed to cover given performance space.
Several examples of state-of-the-art links will be presented throughout
the tutorial, from high-performance DRAM parallel links to serial-links
for high-end router and blade server backplanes.
八、主講人簡介
Prof. Stojanovic received his M.S. and Ph.D. in Electrical Engineering
from Stanford University in 2000 and 2005, respectively. He is currently
an Assistant Professor in the Department of Electrical Engineering and
Computer Science and a member of both Research Laboratory of Electronics
(RLE) and the Microsystems Technology Laboratories (MTL) at the MIT,
where he directs the Integrated Systems Group. Prof. Stojanovic currently
holds a 2006 Doherty Professorship at MIT. From 2001 through 2004, he
was also a principal engineer in Rambus, Inc., Los Altos, CA, where he
made key contributions to Rambus' serial-link technology and patent
portfolio. During 1997-1998, he was a visiting scholar with the Advanced
Computer Systems Engineering Laboratory, Department of Electrical and
Computer Engineering, University of California, Davis.
Please refer to the short course webpage for more information.
http://powereric.ee.ntu.edu.tw/~sscs/lectures/stojanovic/index.html