Trying to allow some instructions to take fewer cycles does not help, since th
e throughput is determined by clock cycle; the number of pipe stages per instr
uction affects latency, not throughput.
第一段話了解，意思應該是每個clock cycle會完成一個指令
讓某些指令走少一些cycle對throughput沒有幫助
分號後那一段覺得不通
Pipeline的stage數，切的數目好壞，有的可能讓latency變更長
這樣throughput不是也會變差嗎？
謝謝！