補充一下，公司有幫忙辦身分，但前提是要有美國合法工作的簽證(OPT/H1-B...)。
我們主要是做ARM CPU的implementation & testchip.
主要是要用先進製程來看能讓ARM CPU的PPA到什麼程度
也會evaluate一些open source的IP，像RISC-V & NVDLA.
有時會需要串一些flow，所以scripting/programming能力希望不要太差。
※ 引述《boy1010 (不要再Q我了 QQ)》之銘言：
: Hi,
: 我們team在找人，傾向找2年以上經驗(2~10yr)的ASIC FE engineer.
: New Grad 也會考慮，如果hiring manager覺得領域及態度符合的話。
: 有意願請站內信。
: Linkedin link: https://bit.ly/2SC0tsN
: Job description
: Job Location: San Jose, California
: Report To: Manager, Test Chip System Design
: Responsibilities:
: Experience with complete ASIC or standard product implementation flow from
: RTL synthesis, design planning, timing analysis / closure, and design
: integrity checking through tape-out
: Requires proficiency with the design tools / flows tcl/perl development
: Desired Skills and Experience
: Requirements:
: Education:
: Master Degree in Electrical Engineering or Computer Science with 2+ years
: ASIC implementation and tape-out experience.
: This position requires thorough knowledge of the ASIC design flow, FE and
: Design verification, synthesis, scripting and netlist generation. The ideal
: candidate will have the following background:
: At least 2+ year experience in ASIC design flow
: Consistent record of RTL design and timing closure on large complex designs
: Expertise in:
: SOC IP integration and RTL Design for performance, low area, and low power
: FE production synthesis and static timing analysis.
: ASIC design flow and netlist flow checks – Synthesis, CDC, Logical
: Equivalence
: UPF flow for power islands as well as voltage islands
: Design interfacing to PD for floorplan and timing closure
: Self-Driven, highly motivated, highly organized, and schedule driven is a must
: Familiarity with DFT and backend related methodology and tools is a plus
: TSMC Technology is an Equal Opportunity Employer.