Introduction
Zyflex, subsidiary of Zyxel group, is a leading company focusing on satellite,
vechiluar, manpack and handheld radios.
We are seeking new members for positions involve the development and design of
wireless communication system on SDR platforms for a variety of wireless modem
products.
Successful applicants will participate in the design, implementation,
integration, and verification of the base-band communication FPGAs.
Digital Logic
Requirement:
- Minimum experience of 2 full years working closely with large FPGAs or ASIC.
Requires a strong digital foundation in design (Verilog), simulation,
synthesis, place/route, integration, and debug.
- Qualifying candidates should be able to quickly assimilate and refine
existing designs; apply test equipment and problem solving skills in the
lab; and maintain designs under revision control.
- Must be a self-starter and team player with a solid understanding of
electrical engineering fundamentals.
- Wired/wireless or telecomm systems experience beneficial.
Responsibilities:
Each person is responsible for 2~3 following items during a project:
- FPGA architecture, micro architecture, RTL design and testbench
emulation.
- Modem timing control and data paths.
- Framers/deframers and data movers.
- Embedded Micro-controller subsystems.
- Peripheral IC driving.
- Contribute to the board design activities
- Work with SW and SI (Verification / integration) team in resolving
SI / FPGA issues.
Baseband Algorithm
Requirement:
Applicants must have a strong background in communication theory and
experienced in at least one following areas:
- Filter design
- Channel Estimation
- Linear/non-linear Equalization
- Synchronization
- Error-Correction Codes
- MIMO Channel
- OFDM/SC-FDM
- CDMA/Spread Spectrum
Two years industry experience in related area.
Familiar with Hardware Description Language is a must.
Responsibilities:
Development and design digital baseband system. Design transmitter and
receiver architecture, functional modeling, and verify. Cooperate with other
engineers for solving issues such like module interface, area optimization and
link performance tuning.
需求人數
4~6名
待遇:
依年資/經驗相關程度 $55000~85000 專案獎金與虛擬股票另計
備註
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