※ 引述《koala0716 ()》之銘言：
: https://drive.google.com/file/d/0B1pKe1BYhAiPbVNhSXRwR0cxT0E/view?usp=sharing
: 不知道是理解還是計算錯誤
: 想了好久一直湊不出答案
: 有請高人指點了
電腦排版 建議用電腦看
看到這題好像沒人解小弟就先拋磚引玉，藉此來讓大家幫小弟修正觀念 : 目
有誤請幫小弟糾正 感謝
A.
┌──────────────────┐
│ ＭＥＭ │
┌────┐│ ┌────┐ ┌───┐│
│ ＣＰＵ ├┼───┤L1 Cache├────┤ＭＥＭ││
└────┘│1 C.C └────┘100 C.C └───┘│
│ │
└──────────────────┘
=> CPI(effective) = 3 C.C = CPI(base) + Memory-stall cycles per instr.
= 1 + Cache access * Miss rate * Miss pently
= 1 * + 1 * x % * 100
=> x = 2 %
=> Hit ratio = 1 - Miss rate = 98 %
Ans : X
B.
1 + 1 * ( 1 - 99.4% ) * 100 C.C.
= 1 + 0.6 / 100 * 100
= 1 + 0.6 = 1.6 C.C.
1 + 1 * ( 1 - 100% ) * 100 C.C.
= 1
the effective CPI ( 1.6 C.C ~ 1 C.C. != 2.5 )
Ans : X
C.
┌────────────────────────────┐
│ 1-X % │
┌────┐│ ┌────┐ 2% ┌────┐ X % ┌───┐│
│ ＣＰＵ ├┼───┤L1 Cache├────┤L2 Cache├────┤ＭＥＭ││
└────┘│1 C.C └────┘ 3 C.C └────┘100 C.C └───┘│
│ │
└────────────────────────────┘
┌L1 hit
Mem access ┤ ┌ L2 hit
└L1 miss ┤
└ L2 miss ─ main MEM
└ (A) ┴ (B) ┴ (C) ┘
Mem access =(A) Cache L1 access times * L1 R/W Cycle +
(B) Cache L2 access times * L1 Miss rate * L2 Cycle +
(C) Cache L2 access times * L1 miss rate * L2 miss rate * Mem Cycle
The 2nd level cache with read / write time = 3 C.C.
The 2nd level cache for an effective time of 2.5 C.C
2.5 = 1 * 1 + 1 * 2% * 3 C.C. + 1 * 2% * X% * 100 C.C.
1.5 = 0.06 + 2X /100
X = 144 / 2
= 72
Hit ratio = 1 - Miss rate = 28%
Ans : X
D.
┌────────────────────────────┐
│ 80 % │
┌────┐│ ┌────┐ 2% ┌────┐ 20 % ┌───┐│
│ ＣＰＵ ├┼───┤L1 Cache├────┤L2 Cache├────┤ＭＥＭ││
└────┘│1 C.C └────┘ x C.C └────┘100 C.C └───┘│
│ │
└────────────────────────────┘
┌L1 hit
Mem access ┤ ┌ L2 hit
└L1 miss ┤
└ L2 miss ─ main MEM
└ (A) ┴ (B) ┴ (C) ┘
Mem access =(A) Cache L1 access times * L1 R/W Cycle +
(B) Cache L2 access times * L1 Miss rate * L2 Cycle +
(C) Cache L2 access times * L1 miss rate * L2 miss rate * Mem Cycle
The 2nd level cache for an effective time of 1.5 C.C
1.5 = 1 * 1 C.C. + 1 * 2% * x C.C. + 1 * 2% * 20% * 100 C.C.
0.5 = 200x /10000 + 4000 / 10000
5000 = 4000 +200x
x = 5
Ans : O
E.
┌────────────────────────────┐
│ 90 % │
┌────┐│ ┌────┐ 2% ┌────┐ 10 % ┌───┐│
│ ＣＰＵ ├┼───┤L1 Cache├────┤L2 Cache├────┤ＭＥＭ││
└────┘│1 C.C └────┘ 4 C.C └────┘100 C.C └───┘│
│ │
└────────────────────────────┘
┌L1 hit
Mem access ┤ ┌ L2 hit
└L1 miss ┤
└ L2 miss ─ main MEM
└ (A) ┴ (B) ┴ (C) ┘
Mem access =(A) Cache L1 access times * L1 R/W Cycle +
(B) Cache L2 access times * L1 Miss rate * L2 Cycle +
(C) Cache L2 access times * L1 miss rate * L2 miss rate * Mem Cycle
The effective time is lower than 1.3 C.C.
1 * 1 C.C. + 1 * 2 % * 4 C.C. + 1 * 2% * 10% * 100C.C.
= 10000 / 10000 + 800 / 10000 + 2000 / 10000
= (10000 + 800 + 2000) / 10000 = 1.28
Ans : O