課程名稱︰電子學二
課程性質︰電機系必修
課程教師︰呂良鴻
開課學院：電資學院
開課系所︰電機工程學系
考試日期（年月日）︰2015/4/22
考試時限（分鐘）：110分鐘
試題 :
圖片檔:http://imgur.com/1fqqOSR,0oKamYR,IpOMJqJ,vTGZxJE,AYavmyx
電子學二 Midterm 2014/4/22
1.
(a) Please conclude the most important reason to use the different circuits istead
of the single-ended ones (3%).
(b) Design the circuit in Fig. 1b to obtain a dc voltage of +0.2V at each of
the drains of Q1 and Q2 when vG1 = vG2 = 0V. Operate all transistors at
Vov=0.2V and assume that for the process technology in which the circuit is
fabricated, Vm=0.5V and uC=250uA/V^2. Neglect channel-length modulation.
Determine the values of R, RD, and the W/L ratio of Q1, Q2, Q3 and Q4.
What is the input common-mode voltage range for your design?(10%)
(c) For each of the emitter-degenerated differential amplifiers shown in
Fig. 1c, find the differential half-circuit and derive expressions for
the differential gain Ad and differential input resistance Rd. For each
circuit, what dc voltage appears across the bias current sources(s) in the
quiescent state(i.e., with vid=0). Hence, which of the two circuits will
allow a larger negative Vcm?(10%)
2.
Fig. 2 shows a Wilson MOS current mirror. All transistors are identical.
(a) Draw a small signal model and calculate the output resistance in
terms of the small signal parameters, transconductors and output resistance,
of the transistors(gm1, gm2, gm3, ro1, ro2, ro3).(8%)
(b) For all transistors, kn'=320uA/V^2, W/L=10, Vt=0.5V, Va'=5V/um, and IREF
=100uA. If we require an output resistance of 500kom, find r0 and channel
length L. For simplicity, you may assume I0=IREF.(8%)
(c) Consider the channel modulation effect and calculate I0/IREF using the
channel length found in (b). Assume VGS3=VGS1. Comment the assumption that
I0=IREF used in (b)(6%).
3.
The circuit in Fig. 3 is a voltage amplifier, where, vi and vo are the input
and output, respecitvely. The parameters are given as VDD=5V, Vtn=|Vtp|=0.5V,
and Van=|Vap|=20V. Assume that all NMOS devices are matched with kn=4mA/V^2
and all PMOS devices are matched with kp=1mA/V^2.
(a) For the amplifier to perate properly, find the expected DC bias voltage
at the input.(5%)
(b) Find the voltage gain Av=v0/vi.(5%)
(c) Find the voltage gain Av1=vd1/vi.(5%)
(d) Find the voltage gain Av3=vd3/vi.(8%)
4.
(32%)(Note: Although this circuit appears in Sec.7.6, strictly speaking you
should be able to answer it adequately using your knowledge gained from
previous sections)
The two-stage CMOS amplifier as shown in Fig.4 below is fabricated with
kn'(=uc)=4kp'=400uA/V^2, Vtn=-Vtp=0.4V.
(a)(3% each, total 24%) With A and B grounded, perform DC biasing design that
will result in each of Q1, Q2, Q3 and Q4 conducting a drain current of 200 uA,
Q6 conducting a drain current of 400uA, and with 0.2V of overdrive voltage for
all eight transistors. Present your W/L results (one single ratio for one W/L
is sufficient, no need to specify the width and the length) for the eight
transistors in table form.
(b) (4%)Perform small-signal analysis first from teh differential input to the
drain of Q2, and then from teh drain of Q2 to the output, to derive the output
voltage gain v0/vi, where vid=vA-vB. Assume all Early voltage to be 5V.
(c) (4%) If Q3 and Q4 are mismatched in their W/L ratio by 5% and Q1 and Q2 are
perfectly matched, estimate the DC offset voltage looking from the input.